In general, a high voltage switching device, provided on an SOI (Silicon On Insulator) substrate, is used at an output stage of a driver IC in a flat panel display such as a plasma display or of an IC for a vehicle. As a certain kind of such a device, an IGBT having a MOS driving device and a bipolar transistor merged together. An IGBT has the advantages of being simple in the arrangement of a driving circuit like a MOS driving device and being low in on-resistance due to conductivity modulation in a voltage blocking section like a bipolar transistor. Therefore an IGBT is regarded as being important in a field requiring a high breakdown voltage and a high electric power level.
In the following, a structure of a related IGBT will be explained. In the specification, a leading character “n” or “p” attached to names of semiconductor layers and regions means that electrons or holes, respectively, are majority carriers in the layers and the regions. Moreover, a sign “+” attached to the leading character “n” or “p” like “n+” or “p+” represents that the impurity concentrations in the semiconductor layer and the region with the sign are comparatively higher than those in layers and regions without the sign, and a sign “−” attached to the leading character “n” or “p” like “n−” or “p−” represents that the impurity concentrations in the semiconductor layer and the region with the sign are comparatively lower than those in layers and regions without the sign.
FIG. 15 is a cross-sectional view showing a structure of a related lateral IGBT. See for example H. Sumida, A. Hirabayashi, and H. Kobayashi, A High-Voltage Lateral IGBT with Significantly Improved On-State Characteristics on SOI for an Advanced PDP Scan Driver IC, 2002 IEEE International SOI Conference, pp. 64-65, 2002. As shown in FIG. 15, an SOI substrate has a structure in which an n− drift region 203 (to be an active region) is layered on a substrate 201 with an insulator film 202 provided between them. Therefore, the insulator film 202 insulates the substrate 201 and the n− drift region 203 from each. In part of the surface layer of the n− drift region 203, a p base region 204 is provided. In part of the surface layer of the p base region 204, an n+ source region 205 and a p+ contact region 206 with a high impurity concentration are provided. The p+ contact region 206 is adjacent to the n+ source region 205. Part of the p+ contact region 206 occupies part of the section beneath the n+ source region 205.
In part of the surface layer of the n− drift region 203, a p+ collector region 207 is provided apart from the p base region 204. Moreover, in the n− drift region 203, an n buffer region 208 is provided to surround the p+ collector region 207. The n buffer region 208 has an impurity concentration higher than that of the n− drift region 203. On the surface of the SOI substrate, an emitter electrode 209 is provided to short circuit the n+ source region 205 and the p+-contact region 206. Over the surfaces of the n− drift region 203, the p base region 204, and the n+ source region 205, a control electrode 211 is provided with an insulator film 210 placed between the electrode 211 and the regions 203, 204, and 205.
As shown in FIG. 15, in the related IGBT 200, a first bipolar transistor is formed with the p base region 204, the n− drift region 203, the n buffer region 208, and the p+ collector region 207. Moreover, a second bipolar transistor is formed with the n+ source region 205, the p base region 204, and the n− drift region 203. The first bipolar transistor and the second bipolar transistor form a parasitic thyristor. For avoiding occurrence of latch-up of the thyristor, restriction is imposed on the upper limit of an on-current.
Several methods are proposed for raising the upper limit of an on-current. D. R. Disney and J. D. Plummer, SOI LIGBT Devices with a Dual P-Well Implant for Improved Latching Characteristics, Proceedings of ISPSD '93, pp. 254-258, 1993, for example, discloses a method of reducing resistance of a path leading from the side of the end of the channel beneath the n+ source region 205 to the p+ contact region 206. According to this method, the operation of the second bipolar transistor can be controlled.
The IEEE publication by Philip K. T. Mok, Azzouz Nazar, and C. André T. Salama, A Self-Aligned Trenched Cathode Lateral Insulated Gate Bipolar Transistor with High Latch-Up Resistance, IEEE Transactions on Electron Devices, Vol. 42, No. 12, pp. 2236-2239, December 1995, for example discloses, eliminating inaccuracy in mask alignment in forming the p+ collector region 207 to minimize the lengths of the paths in the first bipolar transistor and the second bipolar transistor, making the p+ collector region 207 self-aligned with a gate electrode. Furthermore, the IEEE publication by Jun Cai, Johnny K. O. Sin, Philip K. T. Mok, Wai-Tung Ng, and Peter P. T. Lai, A New Lateral Trench-Gate Conductivity Modulated Power Transistor, IEEE Transactions on Electron Devices, Vol. 46, No. 8, pp. 1788-1793, August 1999, for example discloses a method of making most of carriers, flowing into the n− drift region 203 from the p+ collector region 207, reach the p+ contact region 206 without letting the carriers pass through the path in the first bipolar transistor or the second bipolar transistor.
The related lateral IGBT 200 as shown in FIG. 15, however, is prone to an unbalanced electric current distribution in the device even with the use of the methods as described in the above references because most of the current flows on the surface of the device when the device is brought into conduction. This causes the following problems. First, the n− drift region 203 is not uniformly conductivity modulated therein to cause its ON-state Voltage Drop to become higher. Secondly, most of the current flows on the surface of the device, making the current easily flow beneath the n+ source region 205. Thus, the problem of causing latch-up exists. Thirdly, in designing a high breakdown voltage device, the n− drift region 203 is arranged along the surface of the device, requiring a longer n− drift region 203. Therefore, when the related lateral IGBT 200 requires a large amount of current with a high breakdown voltage, there are problems associated with the increased ON-state Voltage Drop and the increased chip area.
For solving such problems, the references JP-A-2-180074 and David Hongfei Lu, Shinichi Jimbo and Naoto Fujishima, A Low On-Resistance High Voltage SOI LIGBT with Oxide Trench in Drift Region and Hole Bypass Gate Configuration, IEEE IEDM Tech Dig., pp. 393-396, 2005, for example, disclose a method of forming an insulator region in the n− drift region 203. According to the method, the n− drift region 203 is made to have a bent configuration to increase its drift length without increasing the horizontal dimensions of the n− drift region 203. Moreover, JP-A-8-88357 (corresponding to U.S. Pat. No. 5,796,125), for example, discloses forming a trench in the n− drift region 203 and forming, under the trench, a by-pass layer of a first conductivity type with the resistivity lower than that of the n− drift region 203. According to this reference, an electron current flows in the by-pass layer, so that the current is not reduced to therefore reduce the ON-state Voltage Drop of the device.
In addition, JP-A-2006-5175, for example, discloses a structure in which a field plate is buried in a trench formed in the n− drift region 203. According to the structure, the electric field strength around the opening of the trench can be lessened.
Furthermore, JP-A-9-74197 (also corresponding to U.S. Pat. No. 5,796,125), for example, discloses forming a gate electrode section to be a trench gate. FIG. 16 is a cross-sectional view showing the structure of a lateral IGBT with its gate electrode section formed to be a trench gate. The lateral IGBT 220 shown in FIG. 16 is, unlike the lateral IGBT 200 shown in FIG. 15, provided with a plurality of trenches 221 that penetrate through the p base region 204 from the surface of the n+ source region 205 and reach the n− drift region 203. According to the method, the total channel width per unit area is increased. Therefore, the electron current from the MOSFET section is increased to reduce an ON-state Voltage Drop. Moreover, in comparison with the lateral IGBT 200 shown in FIG. 15, the current distribution in the device becomes uniform to result in uniform conductivity modulation. This also reduces the ON-state Voltage Drop of the device.
Each of the lateral IGBTs of related art explained above, however, when compared with a vertical IGBT, has a non-uniform current flow in the device with the conductivity modulation becoming also non-uniform. Thus, there are problems of the ON-state Voltage Drop becoming higher and the device breakdown voltage and latch up current becoming lower than those of a vertical IGBT. Moreover, when a component such as a field plate is additionally provided, the structure becomes more complicated, making the fabrication of the device more time-consuming. Furthermore, when a trench is formed in the drift region, the deepened trench depth increases the drift thickness, resulting in a raised ON-state Voltage Drop, which necessitates the depth of the trench to be kept in an adequate range.
There remains a need for a lateral semiconductor device with a low ON-state Voltage Drop and high device breakdown voltage and latch up current. The present invention addresses this need.